Wireless SOC Design Verification Engineer

Wireless SOC Design Verification Engineer As part of our team, you will have the opportunity to verify complex SOCs. Our team integrates multiple sophisticated IP-level DV environments, crafts highly reusable best-in-class UVM Testbenches, implements effective coverage-driven and directed test cases, deploys new tools, and adopts methodologies to improve tape-out readiness. By collaborating with other product development groups across Apple, you can push industry boundaries of wireless systems and enhance the product experience for our customers worldwide. You will learn all aspects of large-scale SOCs, including different architectures, high-speed layered protocols, low-power methodologies, wireless protocols, FW-HW interactions, and multi-chip SOC debug architectures. As a Design Verification Engineer, you'll be central to the verification efforts within our silicon design group, responsible for crafting and productizing state-of-the-art Wireless SOCs. This position involves pre-silicon RTL verification of blocks and top-level SOCs. You should be comfortable with all areas of SOC Design Verification, capable of thriving in a dynamic, multi-functional organization, debating ideas openly, and delivering on complex wireless protocol chip requirements. Description Understand details of High Efficiency SOC Architecture, standard SOC peripherals such as PCIe, Power Management & Low-Power schemes, DMA, CPUs, multi-processor systems, DDR, USB, PLL, power-up, Secured Boot schemes. Deliver power management designs using low-power methodologies and power-up / down scenarios with UPF simulations. Build coverage-driven verification plans from specifications, review, and refine to meet coverage targets. Architect UVM-based highly reusable test benches, integrate complex VIPs, sub-system test benches, and test suites at the SOC level. Achieve targeted coverage and work with design, architecture, software, firmware, and external IP teams to verify the overall SOC design. Collaborate with DV methodology architects to improve verification metrics. Minimum Qualifications BS degree and at least 10 years of relevant industry experience. Preferred Qualifications Hands-on ASIC & SOC DV experience. Sophisticated knowledge of HVL methodology (UVM / OVM), with recent UVM experience. Experience with formal verification is a plus. Proven track record through full ASIC cycle from concept to tape-out, including test planning, testbench implementation, debugging, and coverage closure. Experience taping out large SOC systems with embedded processor cores. Verification experience with PCIe, Bus Fabric, NOC, AHB, AXI in UVM environment. Deep knowledge of low power design, UPF integration, boot-up, power-cycling, HW / FW interaction verification. Low Power Verification experience is a plus. Excellent communication, problem-solving skills, and team collaboration. At Apple, base pay ranges from $175,800 to $312,200, depending on skills, qualifications, experience, and location. Employees can participate in stock programs, receive benefits like medical / dental coverage, retirement plans, educational reimbursement, bonuses, and relocation assistance. Learn more about Apple Benefits. Apple is an equal opportunity employer committed to diversity and inclusion, promoting equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other protected characteristics. #J-18808-Ljbffr