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ASIC Layout Design Engineer
ASIC Layout Design EngineerAkkodis • Louisville, CO, US
ASIC Layout Design Engineer

ASIC Layout Design Engineer

Akkodis • Louisville, CO, US
21 days ago
Job type
  • Permanent
  • Temporary
Job description

ASIC Layout Design Engineer

Location : Louisville, CO

RF Analog ASIC Development

Pay Rate : $75.000 hr. to $100.00+hr. The rate may be negotiable based on experience, education, geographic location, and other factors.

Hybrid Schedule : 3 days a week in-office

  • No Corp-to-Corp; No C2C; No Referrals from C2C

About the Role

Akkodis is seeking a seasoned ASIC Layout Design Engineer to join our clients RF Analog ASIC Development team. This is a 9-month contract with possible extension or conversion to direct hire, The project is focused on spinning an existing ADB converter design. If you've worked on data converters and understand RF and mixed signals, we want to hear from you!

We're looking for someone who not only brings technical expertise but also has a track record of seeing projects through to completion. Speed and reliability matter—so if you stick to schedules and finish what you start, you'll thrive here.

What You'll Do

  • Own cell, block, and chip-level layout in CMOS, BiCMOS, and Bipolar processes
  • Assemble, verify, and debug chip-level designs
  • Lead layout planning and manage internal and external layout teams
  • Develop layout tools and provide training
  • Troubleshoot layout software and manage project databases
  • Drive top-down abstraction and black-box methodology
  • What You Bring

  • 5+ years in RF / Analog / Mixed Signal layout design
  • Strong grasp of layout fundamentals : matching, differential pairs, current mirrors, etc.
  • Proficiency in Cadence Virtuoso, Assura, PVS, Calibre, and layout scripting (Skill, Python
  • preferred)

  • Proficient in broadband RF / high-speed layout, sensitive RF analog matching, and parasitic
  • minimization.

  • Experience with PDKs and multiple foundry processes.
  • Skilled in efficient chip, block, and cell floor planning and signal path optimization.
  • Strong understanding of : Electromigration, Well-proximity and length-of-diffusion effects,
  • Common-centroid matching.

  • Comfortable with arrays, mirrored, and quadrature layouts.
  • Expertise in RF, analog, and digital routing, physical verification, and database management
  • Familiarity with layout of : DAC / ADC, Broadband amplifiers, VGAs, Regulators, VCOs, PLLs,
  • dividers, Samplers, Bandgaps, Charge pumps, IO / ESD structures.

  • Strong understanding of RF, analog, digital, and mixed-signal fundamentals.
  • Someone who is self-sufficient.
  • CAD Tools :

  • Cadence Virtuoso Schematic L, Layout L and XL
  • Physical Verification & Extraction : Cadence Assura, PVS, Pegasus, Mentor Graphics Calibre
  • Design Management : SVN, SOS, Synchronicity, IC Manage (or similar)
  • Programming / Scripting :

  • Skill, Python, Ruby, Shell scripting
  • P-Cell development
  • Bonus :

  • Knowledge of Cadence Allegro PCB Design
  • Soft Skills

  • Excellent communicator and collaborator
  • Strong leadership and mentoring abilities
  • Team-oriented with a proactive mindset
  • If you are interested in this ASIC Layout Design Engineer position in Louisville, CO click apply now.

    Equal Opportunity Employer / Veterans / Disabled

    Benefit offerings availalbe for our associates include medical, dental, vision, life insurance, short-term disability, additional voluntary benefits, an EAP program, commuter benefits and a 401K plan. Our benefit offerings provide employees the flexibility to choose the type of coverage that meets their individual needs. In addition, our associates may be eligible for paid leave including Paid Sick Leave or any other paid leave required by Federal, State or local law, and Holiday pay where applicable. Disclaimer : These benefit offerings do not apply to client-recruited jobs and jobs which are direct hire to a client

    To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit https : / / www.akkodis.com / en / privacy-policy.

    The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and / or security clearance requirements, including, as applicable :

  • The California Fair Chance Act
  • Los Angeles City Fair Chance Ordinance
  • Los Angeles County Fair Chance Ordinance for Employers
  • San Francisco Fair Chance Ordinance
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    Asic Design Engineer • Louisville, CO, US

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