Staff SoC / RTL Design Engineer for Wireless ASICs

A leading tech company in San Diego is seeking a Digital Architect to lead the design and verification of complex ASICs. The ideal candidate will have extensive experience in Verilog RTL coding and a strong background in electrical engineering. Responsibilities include designing hardware that meets performance goals and collaborating with cross-functional teams. This role offers a competitive salary range of $152,566 to $210,000 annually.

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