AI Systems Engineer

Staff Machine Learning Engineer, LLM Fine Tuning (Verilog / RTL Applications) :

HIGHLIGHTS :

• Location : San Jose, CA (Onsite / Hybrid)
• Schedule : Full Time
• Position Type : Contract
• Hourly : BOE

Overview :

Our client is building privacy preserving LLM capabilities that help hardware design teams reason over Verilog / SystemVerilog and RTL artifacts-code generation, refactoring, lint explanation, constraint translation, and spec to RTL assistance. Our client is looking for a Staff level engineer to technically lead a small, high leverage team that fine tunes and productizes LLMs for these workflows in a strict enterprise data privacy environment.

You don't need to be a Verilog / RTL expert to start;curiosity, drive, and deep LLM craftsmanship matter most. Any HDL / EDA fluency is a strong plus.

What you'll do (Responsibilities) :

What you'll bring (Minimum qualifications) :

Nice to have (Preferred qualifications) :

What success looks like :

Baseline an HDL aware eval harness that compiles / simulates;establish secure AWS training & serving environments (VPC only, KMS backed, no public egress).

Expand customization / training coverage (Bedrock for managed FMs including Anthropic;SageMaker / EKS for bespoke / open models).

Demonstrably reduce review / iteration cycles for RTL tasks with clear metrics (defect reduction, time to lint clean, % auto fix suggestions accepted), and a stable MLOps path for continuous improvement.

Customer and internal design data remain within private AWS VPCs;access via IAM roles and audited by CloudTrail;all artifacts encrypted with KMS.

Modeling : PyTorch, HF Transformers / PEFT / TRL, DeepSpeed / FSDP, vLLM, TensorRT LLM

Tooling (nice to have) :

"We are GTN The Go To Network"