Sr.Staff SoC Lead design verification Engineer

Company : Qualcomm Atheros, Inc. Job Area : Engineering Group, Engineering Group >

ASICS Engineering General Summary : As a Design Verification Lead, you will lead a team of ASIC design verification engineers to verify IP and Subsystems that be integrated in a variety of Qualcomm WIFI, connectivity and IOT devices. You will work closely with SoC Architects, software, validation and design teams to verify IP that meets power, performance and area goals for Qualcomm Wireless and connectivity products. You will lead a team defining the processes, methods and tools for design verification of large complex IP blocks and subsystems. Job Responsibilities : Lead Sub-System & SoC Design verification for Qualcomm WIFI projects Own end-end low power test bench architecture, test plan and coverage driven verification closure Collaborate with cross geo teams for various IP, SOC and VI deliveries, milestone planning & critical debugs Build, manage and mentor a team of ASIC DV engineers Explore innovative DV methodologies (formal, simulation, and emulation strategies) to continuously push the quality and efficiency of test benches Act as a technical point of contact to the different IP and SoC design teams Provide technical leadership through personal example, mentorship, and strong teamwork Required Skillset : Experience with various aspects of digital verification such as test automation, code and functional coverage, constraint randomization, system Verilog assertions, and performance. Strong System Verilog / UVM based verification skills, experience with assertions, and coverage-based verification methodology Strong leadership, Analytical and problem-solving skills Experience with C / C++, assembly language. Knowledge of low power design concepts and power management is a big plus. Strong team player and communicator Experience with AMBA bus protocols Experience with GLS, and scripting languages such as Perl, Python is a plus 8+ years or more of practical semiconductor ASIC DV experience including owning end-to-end verification of major SoC blocks 2+ years’ leadership experience taking projects to Tape out Minimum Qualifications :

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. #J-18808-Ljbffr