SoC DFT / DFD Design Verification Engineer, Chiplets (contractor) Boston, Massachusetts, United States

DFT / DFD Design Verification Engineer, Chiplets (contractor)

Tenstorrent is seeking an experienced DFT / DFD Design Verification Engineer for a contract position to support the validation of cutting-edge test architectures in high-performance SoCs. In this role, you will verify Design-for-Test (DFT) and Design-for-Debug (DFD) logic—including JTAG, iJTAG, and internal scan architectures—ensuring robust manufacturability and post-silicon debuggability. You will work closely with DFT architects, RTL designers, and DV teams to develop and execute comprehensive verification plans using industry-standard tools and methodologies.

This is a fixed-term contract role and the candidates can be based in the US or Canada, and we are open to remote work.

Key Responsibilities :

• Define and execute verification plans for DFT / DFD features such as boundary scan, scan chains, and debug logic.
• Develop UVM-based or directed tests to validate IEEE 1149.x (JTAG), 1500 (iJTAG), and 1687 (IJTAG) compliant implementations.
• Verify integration and functionality of ICL (Instrument Connectivity Language) and PDL (Procedure Description Language) content for instrument and test control.
• Simulate and debug DFT / DFD RTL and gate-level designs using industry-standard simulators.
• Collaborate with DFT architecture and implementation teams to ensure functional correctness, performance, and alignment with manufacturability goals.
• Drive coverage closure, including code coverage and functional coverage, across all DFT / DFD blocks.
• Work with post-silicon validation and ATE teams to ensure test vector portability and alignment between simulation and silicon.

Experience & Qualifications :

Tenstorrent is an equal opportunity employer. Compensation details are dependent on experience, skills, education, background and location.

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