Sr FGPA Verification Engineer (Santa Clara County)

Mandate Skills : FPGA

Verification Exp

Strong SystemVerilog Coding

(Universal Verification Methodology)-UVM

JD :

4+ years of FPGA verification experience

Strong SystemVerilog programming skills

Hands-on experience with UVM (Universal Verification Methodology)

Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS)

Experience with code and functional coverage analysis

Proficient in debugging and problem-solving

Scripting experience in Python or Perl

Knowledge of Verilog and / or VHDL