Senior Design Verification Engineer (SystemVerilog & UVM)

A leading tech company in San Francisco seeks a Design Verification Engineer to develop verification methodologies and plans, ensuring the functionality of complex hardware designs. You will work closely with various engineering teams and require a strong background in System Verilog, UVM, and debugging. Candidates should have a Bachelor's degree and at least 7 years of relevant experience. This is an opportunity to contribute to innovative technology in a collaborative environment.

#J-18808-Ljbffr