Editor Jobs in Sunnyvale, CA

About TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now

The Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
• Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

Role Overview

TYLsemi is seeking a Package Design Engineer to own design of IC packages (flip-chip, wirebond and 2.5D/interposer platforms) for high-speed digital and data-center-class products. The successful candidate will drive package design from bump/ball map definition through substrate stack-up, routing, signal/power integrity closure, and tapeout — working closely with SI/PI, silicon design, and test engineering to deliver package designs that are robust against real silicon feedback.

What You’ll Do

• Own end-to-end package design in Cadence Allegro Package Designer (APD) for design feasibility studies through tapeout: bump/UBM mapping, ball map planning, substrate stack-up definition, and fan-out/escape routing.
• Route and close high-speed signal nets (e.g. Parallel interfaces such as UCIe, LPDDR/DDR; SerDes interfaces such as PCIe, Ethernet and UFS) using controlled-impedance and length-matching techniques.
• Design and optimize power delivery networks (PDN) for IC package, including plane splits, decoupling strategy, and via stitching.
• Partner with SI/PI engineering - use SIPI feedback to iterate and harden the package design.
• Drive DRC/DFM closure with substrate vendors; manage design review cycles through tapeout.
• Collaborate cross-functionally with mechanical/thermal/reliability engineering on warpage, CTE mismatch, and underfill selection for package robustness.
• Document design decisions, stack-up specifications, and via schedules for design reuse and knowledge transfer.

Must Have Skills

• Proficiency in Cadence Allegro Package Designer (APD) and associated package layout tools (bump/ball map planning, substrate routing, stack-up definition) for flip-chip/wirebond packaging.
• Demonstrated ability to close package designs against SIPI (signal integrity / power integrity) feedback loops — iterating stack-up, routing, and PDN design based on simulation and/or lab correlation results.
• Solid fundamentals in high-speed digital signal integrity (impedance control, length matching, via stub effects) and power delivery network design.

Qualifications and Bonus Skills

• Typically, 5+ years of relevant experience in IC package design
• Bachelor's or Master's degree in Electrical/Mechanical/Electronics Engineering, or related field.
• Working knowledge of package-level SI/PI, thermal, and mechanical issues.
• Strong analytical and problem-solving skills
• Effective cross-functional communicator, able to work with silicon design, SI/PI, test engineering, mechanical/reliability, and external substrate vendors.
• Experience with Cadence SKILL or equivalent tool for design automation.
• Experience with 2.5D interposer design using Cadence Innovus/Integrity (or equivalent) for silicon interposer / RDL routing.
• Proficiency in Cadence Sigrity/Ansys HFSS/Keysight ADS for package level extraction/analysis of package/interconnect structures.
• Proficiency in Ansys IcePack/Cadence Celsius for package thermal simulation.
• Experience with advanced packaging, Cu Pillar bump technology, and fine-pitch UBM design.
• Working proficiency in Cadence PCB design tools (Allegro X/ PCB Editor / Design Entry HDL) for board-level layout and package-board co-design.
• Familiarity with JEDEC package reliability qualification standards and package-level thermal/mechanical simulation.
• Bonus tools: Cadence Allegro PCB, Cadence Sigrity (PowerDC, PowerSI), Ansys HFSS , Cadence Innovus (2.5D interposer), Keysight ADS.

Compesation

The compensation range shown below represents total target cash compensation and includes both base salary and target bonus. Actual compensation will vary based on factors such as experience, skills, qualifications, job level, and work location.

In addition to cash compensation, this position is eligible for equity in the form of stock options, giving you the opportunity to share in the Company’s long-term growth and success.

The pay range for this role is:
180,000 - 216,000 USD per year(US)

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