Verification engineer Jobs in Minneapolis, MN

Description

Summary : ForwardEdge ASIC is seeking skilled and detail-oriented Design Verification Engineers to join our talent network. As a member of our team, you will play a crucial role in verifying ASIC and FPGA designs for a variety of innovative products. You will collaborate closely with cross-functional teams including digital design, analog design, physical design, and architecture to ensure the quality and functionality of our designs.

Key Responsibilities :

• Collaborate with the ASIC team to understand and verify the functions and requirements of our designs.
• Develop detailed verification plans based on specifications.
• Create verification environments using industry-standard verification languages such as SystemVerilog.
• Implement block-to-top UVM constrained random environments.
• Utilize best practices methodology for functional coverage, assertions, debug, and formal verification.
• Work closely with digital design engineers to achieve comprehensive functional and code coverage metrics.
• Support post-silicon lab validation efforts and handoff.
• Automate processes and methodologies using scripting languages such as Python.
• Other duties as assigned.

Qualifications :

Nice to Have :

Work Environment : The work environment for this role typically involves a combination of office-based activities and collaboration with analog design, CAD, and physical verification teams. Occasional travel may be required for project meetings or customer engagements.

Benefits :