Job Title : RTL Engineer
Location : Sunnyvale, CA
Job Type : Full Time
Job Description :
We are urgently seeking experienced RTL Engineers to join our team. The selected candidates will be responsible for developing and executing verification plans, building robust verification environments, and collaborating closely with design teams to ensure high-quality deliverables.
Responsibilities
- Plan : Develop comprehensive Core Verification Plans based on micro-architecture and design specifications.
- Develop : Architect and implement reusable, scalable verification environments using SystemVerilog / UVM.
- Test : Create and run constrained-random and directed tests to achieve high functional and code coverage.
- Debug : Analyze simulation results, root-cause complex failures, and work with design teams to resolve issues.
- Automate : Build and maintain automation scripts (Python / Perl) to enhance verification workflows and regression management.
Requirements
Mandatory expertise in SystemVerilog and UVM.Minimum 7 years of hands-on verification experience.Strong understanding of digital logic design and verification methodologies.Experience verifying digital systems using standard IP components / interconnects (e.g., microprocessor cores, hierarchical memory subsystems).Ability to work independently and provide technical feedback to FE RTL design teams and CPU / IP micro-architects.Proficiency with industry-standard EDA simulation and debug tools.Strong debugging and root-cause analysis skills.Scripting experience (Python, Perl).Excellent written and verbal communication skills in English.