ASIC Architect

Piper Companies

is seeking an

ASIC Architect

to join a fast-growing innovator in AI infrastructure, for an

onsite permanent

position in

Saratoga, CA

• . The

ASIC Architect

will be l

eadin

g the definition, modeling, and implementation of high-performance ASIC architectures that power next-generation networking and computer systems.

Responsibilities of the ASIC Architect include :

Translate high-level system requirements and application use cases into detailed architecture and functional specifications in collaboration with technical leadership.

Define and align ASIC architecture with system-level goals for performance, power, and efficiency through close coordination with microarchitecture and design teams.

Drive modeling and analysis of datapath behavior to validate architectural decisions, focusing on packet flow, throughput, latency, power, and area trade-offs.

Lead cross-functional collaboration across RTL, Verification, Physical Design, and Firmware to ensure successful implementation, integration, and tape-out readiness.

Qualifications for the ASIC Architect include :

10+ years of ASIC design experience with 5–7 years in true architecture roles across domains such as GPUs, CPUs, DPUs, or networking switches.

Expertise in system-level thinking and architectural modeling, with deep experience in performance analysis, scheduling algorithms, buffering schemes, and high-speed datapaths.

Solid grasp of networking protocols (e.g., Ethernet, TCP / IP, MPLS, RoCE) and hardware-software interface design, including high-speed I / O integration like PCIe and SerDes.

Proven ability to work across the ASIC lifecycle from concept to validation, with a methodical approach to solving complex design and system challenges.

Compensation for the ASIC Architect :

$270,000-$290,000 / year

Medical, Dental, Vision, sick leave if required by law, and 401K

This job opens for applications on 8 / 15 / 25. Applications for this job will be accepted for at least 30 days from the posting date.

Keywords

ASIC Architecture, Networking ASIC, RTL Design, SerDes, PCIe Gen5, PCIe Gen6, High-Speed Datapath, Microarchitecture, System-on-Chip (SoC), Packet Processing, Memory Crossbar, Buffering Schemes, Scheduling Algorithms, Performance Modeling, Ethernet, TCP / IP, UDP, VLAN, MPLS, RoCE, Control Plane Architecture, High-Performance Computing, Switching Architecture, Architecture Behavioral Modeling, Hardware / Firmware Integration, Physical Design Constraints, Queuing Theory, System Architecture, Network Protocol Offload, DPU, GPU Architecture, CPU Architecture, IP Integration

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