SOC Static Timing Analysis Engineer - Full Time

Job Description

Job Description

Join a cutting-edge and well-funded hardware startup in Silicon Valley as a Silicon STA Engineer. Our mission is to reimagine silicon and create Risc-V based computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

Responsibilities

• Block level and / or full chip timing analysis throughout the life cycle of a project, from early investigation to final implementation and tapeout
• Develop our timing methodology and infrastructure to support the timing flow from RTL synthesis to implementation and timing closure
• Work with architects and logic designers to generate block and full chip timing constraints
• Work with system and technology teams to define analysis scenarios and margining strategies
• Develop a rigorous and comprehensive signoff methodology to guarantee high quality robust silicon
• Partner with physical design teams to close and sign off the designs

Requirements

Education and Experience

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.