Principal ASIC Design Engineer

Synaptics Inc.San Jose, CA, US

16 days ago

Job type

Full-time

Job description

Description

Synaptics is leading the charge in AI at the Edge, bringing AI closer to end users and transforming how we engage with intelligent connected devices, whether at home, at work, or on the move. As the go-to partner for the world’s most forward-thinking product innovators, Synaptics powers the future with its cutting-edge Synaptics Astra™ AI-Native embedded compute, Veros™ wireless connectivity, and multimodal sensing solutions. We’re making the digital experience smarter, faster, more intuitive, secure, and seamless. From touch, display, and biometrics to AI-driven wireless connectivity, video, vision, audio, speech, and security processing, Synaptics is the force behind the next generation of technology enhancing how we live, work, and play.

Overview

Synaptics is looking for a highly experienced Principal ASIC Design Engineer to provide technical leadership and architectural expertise. This role requires deep knowledge of digital design methodologies, strong problem-solving skills, and the ability to guide cross-functional teams through complex design and verification challenges. This role will play a key role in driving innovation, ensuring design quality, and influencing the strategic direction of ASIC development. This position reports to the Sr. Director, ASIC Design.

The typical base pay range for this position is USD $182,000 - $286,000 per year. Individual pay is determined by many factors including work location, job-related skills, experience, and relevant education or training. This position is also eligible for a discretionary annual performance bonus, equity, and other benefits. Note that compensation listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

Responsibilities & Competencies

Job Duties

Lead the architecture, design, and implementation of complex ASICs from concept through production
Define design specifications, micro-architecture, and system-level interfaces in collaboration with system architects, firmware / software teams, and hardware engineers
Responsible for SoC-level integration of high-speed interface IPs (PCIe, USB, HDMI, MIPI) and end-to-end support through pre-silicon verification and post-silicon bring-up
Drive tradeoff analyses across power, performance, area, and cost (PPA) to ensure optimal design solutions
Oversee RTL coding, synthesis, linting, and static timing analysis, ensuring high-quality, reusable, and scalable designs
Guide verification planning and methodologies, collaborating closely with the verification team to ensure functional correctness and coverage closure
Partner with physical design teams to resolve timing, floorplanning, and power optimization challenges
Serve as the technical point of escalation for complex design / debug issues, providing hands-on problem-solving support
Evaluate and adopt advanced design methodologies, tools, and flows to improve efficiency and quality
Mentor junior engineers, setting best practices in coding standards, design reviews, and documentation
Collaborate with product and program management to align design activities with project schedules, milestones, and deliverables
Contribute to customer and partner engagements, providing technical expertise and influencing product direction

Competencies

Expert knowledge of ASIC / SoC design methodologies, digital logic design, and micro-architecture development

Strong proficiency in RTL coding (Verilog / SystemVerilog, VHDL) and simulation environments

Strong knowledge of Perl / Python, Shell scripting

Deep understanding of synthesis, static timing analysis, DFT, and low-power design techniques

Familiarity with physical design flows, constraints, and close interaction between front-end and back-end teams

Analytical and data-driven decision-making, with the ability to balance tradeoffs in complex systems.

Ability to communicate complex, interactive design concepts clearly

Proactive, self-starter, able to work independently in a fast-paced environment to complete projects on time with minimal guidance

Well organized with strong attention to detail; proactively ensures work is accurate

Positive attitude and work ethic; unafraid to ask questions and explore new ideas

Resourceful and able to solve highly complex problems through adaptation of existing technology and development of new technology with a deep understanding of product architecture

Strong communication and team leadership skills to ensure effective cross-functional collaboration and customer engagement

Ability to work within a diverse team and mentor developing team members

Qualifications (Requirements)

Bachelor’s degree (advanced degree preferred) in Electrical Engineering, Computer Engineering, or related field, or equivalent

15+ years of experience in ASIC / SoC design, with at least 5 years in a technical leadership or architect-level role

Proven track record of delivering high-performance ASIC designs to production

Experience with industry-standard design and verification tools (e.g., Synopsys, Cadence, Mentor Graphics)

Hands on experience with Logic Synthesis using Design Compiler, Static Timing Analysis with Prime Time and low-power design techniques / flows

Excellent pre-silicon and post-silicon debugging skills and root-cause analysis of complex design issues at block and system levels

Understanding of firmware / software interaction with hardware, system-level integration, and bring-up

Minimal travel up to 10%

Belief in Diversity

Synaptics is an Equal Opportunity Employer committed to workforce diversity. Qualified applicants will receive consideration without regard to race, sex, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, or genetic information.

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Asic Design Engineer • San Jose, CA, US