ASIC Design Engineer : RTL & Micro-Architecture

A leading telecommunications firm in San Jose is looking for an ASIC Design Engineer to work closely with system architects on defining micro-architectures and RTL development. Candidates should have a Bachelor's degree in Computer Science or Electrical Engineering and at least 1 year of relevant experience. Strong skills in ASIC / FPGA design, Verilog / SystemVerilog, and scripting languages are required. This role offers opportunities for optimization and problem-solving in a collaborative environment.

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