Analog Layout Design Summer 2026 Intern

Description

·Pursuing BSEE, MSEE

·Exposure to microelectronics design and requirements

·Understanding of layout effects on the circuit such as speed, capacitance, power and area etc.,

·Knowledge of various analog layout techniques like matching, shielding etc.,

·Exposure to Cadence Virtuoso Layout and physical verification tools is a plus

·Team player, driven, self-motivated and autonomous

·Excellent communication, presentation and customer service skills

We’re doing work that matters. Help us solve what others can’t.