Post-Silicon Validation Engineer

Job Description

Job Description

Post-Silicon Validation Engineer

About Etched

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers from NVIDIA, Google, and Meta, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a highly skilled and motivated Post Silicon Validation Engineer to join our dynamic team. The ideal candidate will be responsible for bringing up, validating, and characterizing ASICs from first silicon through the production ramp. This role is crucial in ensuring functional correctness, performance, and reliability of our AI / ML accelerator hardware, enabling successful deployment of our cutting-edge products.

Key Responsibilities

Silicon Bring-Up & Debug

Drive early bring-up of first silicon, including boot, initialization, and debug of ASICs.

Perform deep-dive debug of silicon issues across RTL, firmware, and system levels.

Collaborate closely with design, verification, and board teams to root-cause and resolve functional and electrical issues.

IP Validation & Characterization

Validate and characterize custom IP blocks and accelerator components.

Execute functional and performance validation of compute units and specialized processing elements.

Conduct IP-level and full-chip stress testing and corner case analysis to ensure robust operation.

Infrastructure & Automation

Develop and extend post-silicon validation infrastructure, automation, and test suites.

Implement efficient result capture, analysis, and regression frameworks.

Utilize lab instrumentation (oscilloscopes, analyzers, BERTs, pattern generators) for detailed signal and system characterization.

Cross-Functional Collaboration

Define validation strategies and coverage metrics across design blocks and subsystems.

Partner with RTL, DFT, ATE, firmware, and system architecture teams to ensure smooth transition from pre-silicon verification to post-silicon validation.

Provide critical feedback on test escapes, yield issues, and silicon errata, influencing silicon revisions and firmware / driver workarounds.

You may be a good fit if you have

7+ years of experience in post-silicon validation, bring-up, and debug of ASICs (preferably including AI / ML accelerators)

Proven expertise in early silicon bring-up, debug, and validation

Deep knowledge of peripheral interfaces and board-level debug

Proficiency in C, Python, and scripting for validation automation

Hands-on expertise with oscilloscopes, logic / protocol analyzers, and other validation lab tools

Familiarity with firmware, bootloaders, and low-level silicon debug environments

Strong problem-solving, analytical, and collaboration skills across hardware and software teams

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's preferred)

Strong candidates may also have experience with

Low-speed peripheral interfaces (I2C, SPI, UART, JTAG)

High-speed protocols (PCIe, Ethernet)

Memory subsystems (HBM, DDR)

Performance and thermal characterization

AI / ML model profiling and workload correlation

System-level validation of accelerators or server platforms

Base Salary Compensation

$160,000 - $260,000

Benefits

Full medical, dental, and vision packages, with generous premium coverage

Housing subsidy of $2,000 / month for those living within walking distance of the office

Daily lunch and dinner in our office

Relocation support for those moving to San Jose (Santana Row)

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Compensation Range : $160K - $260K