DDr5 verification design ENG - Santa Clara, CA - AMDJP00004484

Hi

Role : ASIC / RTL Design Engineer

Location : Santa Clara, CA

Contract

THE ROLE :

We are looking for an adaptive, self-motivative Design Verification Engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve abilities to deliver the highest quality, industry-leading technologies to market. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.

THE PERSON :

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites / time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES :

• Develop / Maintain tests for functional verification.
• Build the directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues.
• Work on functional & code coverage verification.
• Provide technical support to other teams

PREFERRED EXPERIENCE :

ACADEMIC CREDENTIALS :