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Principal Layout Designer (I / O Layout Design - FPGA)

Principal Layout Designer (I / O Layout Design - FPGA)

Microchip Technology IncSan Jose, CA, United States
7 days ago
Job type
  • Full-time
Job description

Overview

Microchip Technology Inc. has a Principal I / O Layout Design Engineer opening based in San Jose, CA. This engineer will be responsible for layout design, integration, and verification of complex analog circuitry (clocking, Rx, Tx) integrated into the I / O's of the FPGA.

Responsibilities

  • Layout complex analog circuits for GPIO, HSIO, high-speed DDR and other IO applications in advanced FinFET nodes.
  • Collaborate closely with the design leads to understand the design requirements and implement them in layout to meet performance specs.
  • Ownership of both I / O block level and top-level layout of complex I / O blocks to be integrated at chip top.
  • Work closely with the I / O layout lead and ASIC team to optimize IO floor plan, placement and routing of power and critical signals.
  • Run ERC, DRC, LVS and EMIR and other checks. The ability to customize DRC and LVS decks is a plus.
  • Layout guidance and mentorship of junior engineers.

Qualifications

  • Bachelor's in Electrical Engineering, Physics, Computer Engineering or Computer Science preferred.
  • 8+ years of proven silicon mask design experience in design of high-speed IOs in multiple technology nodes.
  • Familiarity with FinFet technology. Knowledgeable about industry standard tools like Virtuoso, skill scripting, Calibre, etc.
  • Proven experience delivering multiple layout designs of complex macros like PLL, I / Os, SerDes to be integrated at SoC level.
  • Experience in high-speed layout design techniques (DDRx, PCI-e, USB, MIPI).
  • Demonstrated competency in scripting using skill, Python and Perl.
  • Good analytical, oral and written communication skills.
  • Able to write clean, readable presentations.
  • Self-motivated, proactive team player.
  • Ability to work to schedule requirements.

    • Travel Time : 0% - 25%

    Physical Attributes : Feeling, Hearing, Seeing, Talking, Works Alone, Works Around Others

    Physical Requirements : 15% standing, 15% walking, 70% sitting, 100% In doors; Usual business hours

    Pay Range : We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below :

    Benefits of working at Microchip

    The annual base salary range for this position, which could be performed in California, is $70,000 - $163,000.

  • Range is dependent on numerous factors including job location, skills and experience.

    • Microchip Technology Inc is an equal opportunity / affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

    For more information on applicable equal employment regulations, please refer to the Know Your Rights : Workplace Discrimination is Illegal Poster.

    To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

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    Layout Designer • San Jose, CA, United States