FPGA Verification Engineer

Overview

FPGA Verification Engineer / Technical Lead II – VLSI role at UST. The candidate will work on verification of complex FPGA designs, ensuring functionality, performance, and reliability, and collaborate with design engineers to develop verification plans, identify and debug issues, and contribute to overall product quality.

Role Description

FPGA Verification Engineer

• Technical Lead II – VLSI

The Opportunity

This position description identifies the responsibilities and tasks typically associated with the performance of the position. Other relevant essential functions may be required.

What You Need

Compensation & Location

Role Location : California

Compensation Range : $101,000 - $152,000

Note : Compensation can differ based on location, role, skill set, education, and experience.

Benefits

Full-time employees accrue paid vacation, sick leave, holidays, and may participate in the 401(k) retirement plan with employer matching. Medical, dental, and vision insurance are available, along with life insurance, accidental death and disability insurance, and disability benefits. Various health account options (HSA / FSAs) may be available. Benefits vary by location.

What We Believe

We proudly embrace the values of Humility, Humanity, and Integrity. We strive for a people-first, human-centered culture that prioritizes sustainable solutions and keeps our people and clients at the forefront of decisions.

Equal Employment Opportunity Statement

UST is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected characteristics. We consider applicants with arrest or conviction records in accordance with state and local laws and fair chance ordinances.

Additional Information

UST

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