SOC Physical Design - Full time

Job Description

Job Description

Positions are open for full-time and co-op / internship in the areas of SOC physical implementation from unit level to chip level, involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power.

Responsibilities

• Own block level design from RTL-to-GDSII and drive synthesis, floor-planning, place & route, timing closure, and signoff.
• Work extensively with Micro-architects to perform feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure.
• Develop physical design methodologies and customize recipes across various implementation steps to optimize PPA.
• Work with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as Timing, Power, EM / IR, PDV.

Requirements

Education and Experience

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.