Senior SoC & RTL Design Engineer for Wireless ASICs

A leading technology company in California is seeking an experienced engineer to lead the design and verification of next-generation ASICs. The ideal candidate will have a Master's or Bachelor's degree in Electrical Engineering and significant experience in digital architecture and Verilog RTL coding. The role involves collaborating with cross-functional teams to ensure successful integration into SoCs for mobile applications. This position offers a competitive salary ranging from $152,566 to $210,000 annually.

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