dft engineer - 1293079

Job Description

Job Description

DFT Engineer

Responsibilities

• Define & document DFT requirements / Specifications for IP / Block and Chip level
• Execute DFT Lint to identify scan DRC violations and resolution
• Top level and hard macro block level scan insertion with high EDT compression ratio (Hybrid LBIST, EDT IP / ATPG, LPCT EDT, AC scan verification with high speed PLL, MBIST, and IJTAG)
• Plan and Insert MBIST and memory repair (BISR) at RTL
• Generate and port IJTAG ICL / PDL and STIL patterns for MBIST, ATPG, and JTAG tests
• ATPG pattern verification on pre / post-route gate-level netlist including 0-delay and SDF
• Work with backend team for the MBIST / Scan mode constraints generation, scan reorder, VCDs for IR drop analysis during DFT, ECO changes and formal verification (LEC), and timing closure
• Support test engineer for pattern generation, tester debug and failure analysis.
• Work with Test Engineering team during Silicon bring-up and creating flow / scripts necessary for debugging / diagnosing compression LPC ATPG patterns (stuck-at / at speed), MBIST patterns on ATE for development and production programs
• Expert knowledge of Mentor Tessent toolchain

Job Requirements