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Engineer II - Validation
Engineer II - ValidationMicrochip Technology • 3850 N. First St, San Jose, CA
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Engineer II - Validation

Engineer II - Validation

Microchip Technology • 3850 N. First St, San Jose, CA
30+ days ago
Job type
  • Full-time
Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our ; we affectionately refer to it as the and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over without a great team dedicated to empowering innovation. People like you.

Visit our page to see what exciting opportunities and company await!

Job Description:

Microchip has been consistently recognized as one of the best places to work by prestigious publications like Forbes, Bay Area News and Phoenix Business Journal. The FPGA Business Unit (formerly Actel, with a 35+ year uninterrupted legacy of providing programmable logic solutions) is one of the largest and most profitable BUs inside Microchip. We have revolutionized the FPGA industry with the industry’s most awarded FPGA families - the PolarFire FPGA family and the first RISC-V based PolarFire SoC, delivering class leading power efficiency, reliability and security. With this portfolio, we have enabled commercial applications like the world’s most innovative AI-enabled embedded vision and smart automation products, the world’s most secure and reliable 5G communications networks, as well as the world’s most sophisticated aerospace products that have delivered payloads to Mars and beyond. If you are looking to be a part of a team that is transforming the world of low power compute whilst delivering exceptional top line growth rates, you will be challenged to find a better place to contribute, grow your career and learn to deliver truly remarkable solutions. The successful candidate will be responsible for the following,

  • Use FPGAs to create systems level designs to bring up and debug use models in the lab.

  • Architecture definition and FPGA design creation utilizing all hardware features and IP cores targeted to existing and future Microchip products.

  • System and FPGA design must exercise all the use models targeted for each product mimicking end applications in a customer setting.

  • Develop high level system and product level validation plans for new and existing silicon products and projects, execute per plan. Review dependencies, estimate effort and identify and communicate risk.

  • Understand hardware architectures, define use models and execute / oversee system level design implementations required to utilize the silicon features.

  • Be an effective contributor in a cross-functional team-oriented environment.

  • Write high quality code in Verilog, VHDL and C code. Maintain existing code.

  • Support regression and re-use.

  • Learn new system designs and validation methodologies.

  • Understand FPGA architectures.

  • Collaborate with cross-functional managers/teams to identify and resolve inter-dependencies.

  • Define and improve processes followed in the department; follow quality metrics and assess per project.

  • Must be willing to take late night or early morning calls to interface with engineers working in India Standard Time zone, when and if required.

Requirements/Qualifications:

  • Bachelors or Masters in EE/CE with 0 to 3 years of experience.

  • Knowledge of FPGA architectures is a must.

  • Possess an understanding of hardware architectures, system level IC design implementation, and knowledge of how to create end use scenarios.

  • Design with RTL coding in Verilog or VHDL is a must.

  • Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools.

  • Technical background in FPGA prototype emulation, and debug.

  • Technical background in silicon validation, failure analysis and debug.

  • Knowledge and experience in embedded firmware development and bringup in the lab

  • Demonstrate board level debug capabilities in lab environment: hands-on troubleshooting skills for digital logic and analog circuit on PCBs using oscilloscopes, digital analyzers, protocol exercisers and analyzers, FPGA integrated logic analyzers (e.g. Synopsys Identify, Xilinx Chip scope, Altera Signalscope, Lattice Reveal).

  • Good knowledge of validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART, Ethernet, PCI and USB.

  • Strong commitment to quality and customer satisfaction.

  • Excellent verbal and written communication skills.

  • Able to travel 0-2 times annually if required.


Preferred qualifications:

  • C, C++ or object-oriented programming skills is desirable.

  • Knowledge of RISC-V architecture and Instruction Set is desirable.

  • Knowledge of PERL/TCL/python scripting is desirable.

  • Knowledge and experience in JTAG, SVF and 1532 standards and STAPL programming is desirable.

  • Familiarity with any high speed SERDES controllers that make use of 12Gbps PCS, PMA is a big plus

  • PCIe Gen1/2/3

  • Ethernet 10/100/1000 Mbps : Triple Speed Ethernet MAC

  • Ethernet 1/2.5/10G [RGMII, (Q/)SGMII, USXGMII]

  • Ethernet IEEE702.3dm

  • Ethernet Sync-E (Synchronous Ethernet), Time Sensitive Networks

  • Video interfaces SDI-SD/HD/3GHD and SDI (5.94, 11.88Gbps), Displayport (6.48 to 10Gbps), HDMI (3.96 to 6 Gbps), HBR3(8.1 Gbps), MIPI C-PHY & D-PHY 1Gbps/lane

  • Design and debug experience for any of the below high-speed serial communications protocols is a plus:

  • USB 3.1,3.2

  • CoaXpress (12.5G)

  • CXP(10G)

  • OctalSPI

  • I3C, PMBUS, I2S

  • CAN

Miscellaneous:

  • Embedded Non-Volatile Memories


Percentage of time spent:

  • Documentation – 20%

  • Design Creation & Verification – 30%

  • Lab Bringup & Debug – 50%

Travel Time:

0% - 25%

Physical Attributes:

Feeling, Handling, Hearing, Other, Reaching, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements:

70% sitting, 15% standing and 15% walking, 100% indoors; Usual business hours

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:The annual base salary range for this position, which could be performed in the US, is $70,304 - $143,000.*

*Range is dependent on numerous factors including job location, skills and experience.

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

For more information on applicable equal employment regulations, please refer to the .

To all recruitment agencies:

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Engineer II - Validation • 3850 N. First St, San Jose, CA

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