Design Verification Engineer

Title

Design Verification Engineer – Internal IP

Location

Bay Area (hybrid) or Toronto

About the Company

A fast-growing AI startup designing next-generation compute hardware. The company specializes in building high-performance IP blocks and accelerators, aiming to enable leading‑edge AI workloads with custom silicon and software stacks.

Role Overview

You will lead verification efforts on internal IP blocks that power the company’s compute architecture. Working closely with design engineers and systems teams, you’ll define verification strategies, develop testbenches, write directed and random stimulus, debug failures, and sign off quality IP for integration into larger systems.

Key Responsibilities

• Review IP specifications and architecture to understand functional, performance, and integration requirements.
• Develop verification plans, create functional coverage models, define corner cases and failure modes.
• Build testbenches using SystemVerilog (or similar HDL), UVM or equivalent methodology, and integrate into simulation / acceleration / emulation flows.
• Automate regressions, monitor coverage metrics, identify gaps, and work with design teams to close them.
• Debug and triage simulation / emulation failures, analyze waveforms / traces, provide meaningful feedback to design and physical teams.
• Collaborate with RTL designers, synthesis and physical teams, CAD and systems / firmware teams to ensure smooth handoff and tape‑out readiness.
• Mentor or collaborate with other engineers to drive verification best practices and process improvements.

Qualifications

Nice to Have

What’s in It for You

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