Senior RTL Design Engineer - Low-Power ML Accelerators

A leading tech company in Sunnyvale, CA is looking for an engineer to help shape the future of AI / ML hardware acceleration. This role involves driving power efficiency for Tensor Processing Unit (TPU) designs, defining methodologies for low-power RTL designs, and collaborating with cross-functional teams. The ideal candidate should have a background in electrical engineering and significant experience in digital ASIC design, with a competitive salary of $156,000-$229,000 plus benefits.

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