Design Verification Engineer

San Francisco Bay Area, California, United States Hardware

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily.This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to : establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Description

In this role, you will be responsible for ensuring bug‑free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro‑architecture. You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. A mindset to break the design is highly desirable. Furthermore, you will develop verification plans for all features under your care, execute verification plans, including design bring‑up, DV environment bring‑up, regression enabling features, and debug of the test failures. You will also learn to develop block, IP and SoC level test‑benches track and report DV progress using a variety of metrics, including bugs and coverage. You will also be expected to make use of LLM and related technologies to achieve efficient execution and improved quality.

Responsibilities

Study design specification and create test plan

Develop infrastructure in SystemVerilog / UVM to stress the design

Develop and fix failures from regressions, close bugs

Use LLMs to do verification efficiently

Minimum Qualifications

BS degree in technical subject area and a minimum 10 years relevant industry experience.

Preferred Qualifications

Deep knowledge of OOP, SystemVerilog and UVM

Deep knowledge in developing scalable and portable test‑benches

Strong experience with verification methodologies and tools such as simulators, waveform viewers, Build and run automation, coverage collection, gate level simulations

Working experience using LLMs for efficiency and quality

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