Senior Design Verification Engineer

A company is looking for a Senior Design Verification Engineer.

Key Responsibilities

Own verification of IP's and SoC's in prototype and SoC design environment

Establish functional and performance benchmarks

Lead the definition, execution, and continuous improvement of a robust design verification methodology and tools flow

Required Qualifications

Sound knowledge of System Verilog with experience in constrained Random and Coverage Driven Verification using UVM / OVM

Experience in creating UVC components or sequences

Basic knowledge of at least two protocols such as AHB / AXI, PCIe / CXL, USB, DDR, or Serial protocols, with expertise in one protocol required for senior level

Comfortable updating existing verification environments for feature updates

Good knowledge of Perl / TCL / Python scripting