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Senior Verification Engineer
Senior Verification EngineerInfineon Technologies • Andover, MA, US
Senior Verification Engineer

Senior Verification Engineer

Infineon Technologies • Andover, MA, US
1 day ago
Job type
  • Full-time
Job description

Overview

Join to apply for the Senior Verification Engineer role at Infineon Technologies

Infineon Technologies provided pay range

This range is provided by Infineon Technologies. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$117,800.00 / yr - $162,200.00 / yr

Responsibilities

  • Generate VerilogAMS / systemVerilog models and correlate results with schematic level performance using appropriate test benches
  • Coordinate with team members on the Design Entry, Development, and Implementation of custom AMS behavioral models and schematic netlisting for the purpose of performing high-quality pre-silicon verification of Engineering and Production ICs.
  • Generate tests and perform verification of mixed signal designs utilizing both Cadence's ADE Explorer and Xcelium Suite of tools.
  • Generate simulation workbenches and interpret the results to verify compliance with both device-level and system-level requirements.
  • Contribute, support and perform verification of DFT plans that may include support for digital scan chain testing.
  • Contribute, support and perform verification of functionality performances, as well as ATE and Bench testability of Production ICs.
  • Collaborate with various teams on the Design, Development and Verification of Engineering and Production ICs.

Qualifications

  • BSEE / ME or equivalent with 3+ years' experience as a Verification Engineer.
  • Experienced with Cadence Virtuoso and Xcelium Tool Suite driven by the Hierarchy Configurations.
  • Capable of creating schematics and generating netlist for simulation.
  • Good understanding of analog design techniques.
  • Understanding the signal flow and boundaries between the analog and digital domains.
  • Extensive experience in the compiling, elaborating, and running of mixed-signal simulation in both ADE Explorer and Xcelium.
  • Solid understanding of analog Spectre simulation and associated AMS modeling of analog circuit blocks.
  • Solid debugging skills in both the analog and digital domains.
  • Conversant in Verilog, Python, C, C++ and capable of generating simple scripts.
  • Experience with Microsoft Office Tools (Word, Powerpoint, Excel) and Unix / Linux shell commands and editors.
  • Experienced with version control systems.
  • Experienced with bug reporting and tracking systems.
  • Work well with teams but also a self-starter
  • Employment type

  • Full-time
  • Industry

  • Semiconductor Manufacturing
  • J-18808-Ljbffr

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    Verification Engineer • Andover, MA, US

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