Sr. CMOS IC Layout Engineer
Red Cell Partners is an incubation firm building and investing in rapidly scalable technology-led companies that are bringing revolutionary advancements to market in three distinct practice areas : healthcare, cyber, and national security. United by a shared sense of duty and deep belief in the power of innovation, Red Cell is developing powerful tools and solutions to address our Nation's most pressing problems.
About The Role
We are seeking a highly motivated Digital Verification Engineer to join our team developing digitally integrated circuits for Power Management Integrated Circuits (PMICs). These designs are at the core of high-efficiency energy solutions across a wide range of applications, from mobile and automotive to enterprise and IoT systems.
As a member of the team, you'll ensure the functional correctness, robustness, and performance of our digital IP blocks and subsystems before silicon tape-out. You'll work closely with design, architecture, and validation teams to verify critical control logic, digital interfaces, and mixed-signal interactions within the PMIC domain.
While familiarity and experience with UVM (Universal Verification Methodology) is a plus, it is not fully required. We are looking for candidates with a solid foundation in functional verification and a strong interest in working on mission-critical power management designs.
What You Will Do
What You Will Bring
What Is Helpful
We're an Equal Opportunity Employer : You'll receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.
Layout Engineer • Torrance, CA, United States