Overview
Full-time : Salary + Benefits + Bonuses / Contractor
Location : San Jose CA / Remote
About the Role
The ASIC Verification Engineer will play a crucial role in executing a comprehensive test strategy for future ASIC development. You will be part of a team creating automated regression suites, executing verification methodologies.
Responsibilities
As our ASIC Design Verification Engineer, you will :
Collaborate with design and other verification engineers to develop and execute test strategies.
Write testbenches and test cases based on test plans.
Develop and improve UVM frameworks.
Contribute to unit-level and system-level verification deliverables.
Become a key contributor to ourASIC verification framework, methodology, and test automation.
Implement DSP verification environments to facilitate testing of the RTL against reference MATLAB and Python models
Testing & Automation
Run and automate regression tests.
Analyze code and functional coverage and provide actionable feedback to the development and verification team.
Prepare and present detailed reports on testing outcomes and verification strategies.
Qualifications
Qualities of a Successful Candidate :
BS or MS in Electrical / Computer Engineering or equivalent.
10+ years of experience in ASIC verification.
Proficiency in SystemVerilog and UVM for verification.
Knowledge of verification for DSP algorithms and Mixed Signal systems.
Nice to Have
Familiarity with Cadence Xcelium simulators or similar tools.
Knowledge of scripting languages such as Python or TCL.
Experience working on Linux-based systems.
Compensation & Benefits
The anticipated annual base salary for this position is between $135,000 to $165,000, which also includes a comprehensive benefits package.
15 days of PTO per calendar year
10 paid Holidays per calendar year
Comprehensive Medical Benefits : Company covers 80% of premiums for Employee and Dependents
Dental & Vision : Company covers 50% of premiums for Employee and Dependents
Voluntary Benefits : Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
Life / AD&D and Long-Term Disability
Equal Opportunity
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Social
LinkedIn : https : / / www.linkedin.com / in / rtl2gds /
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Sr Design Verification Engineer DSP • San Francisco, California, United States