Design Verification Engineer - SoC

Overview

Job DescriptionDV Engineer - SoC (Systems / Performance)

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video models and extremely deep & parallel chain-of-thought reasoning agents.

Responsibilities

As a DV Engineer (Systems / Performance) owning the verification of a certain area of performance features in an ASIC design, you will have responsibilities as follows :

Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon).

Work closely with software and application developers on identifying performance bottlenecks and tuning the software.

Develop test plans and test infrastructure / tools for performance tuning, correlation, and verification.

Improve and maintain the architectural performance models.

Develop tests in SystemVerilog , Python , or vectors to debug and correlate the RTL and performance model.

Develop SystemVerilog or Python-based checkers for verifying the performance features.

Develop coverage monitors and analyze coverage to ensure all performance features are covered.

Debug performance issues and conduct performance tuning on silicon.

Drive end-to-end performance tuning , ensuring optimal hardware utilization, software efficiency, and architectural alignment across the ASIC design lifecycle.

Qualifications

You may be a good fit if you have (Must-have qualifications)

ASIC / SoC Design & Verification Experience

Strong understanding of digital design, RTL, and ASIC design flows.

Hands-on experience with performance verification, simulation, and modeling.

SystemVerilog & Python Expertise

Comfortable developing checkers, coverage monitors, and testbenches in SystemVerilog.

Skilled in writing Python scripts for automation, data analysis, and performance modeling.

Architecture & Performance Modeling Knowledge

Experience building and maintaining performance models for chip subsystems.

Understanding of memory hierarchies, pipelines, interconnects, and compute accelerators.

Software Performance Profiling

Familiarity with performance bottleneck analysis, compiler optimizations, and workload tuning

Some exposure to kernel level performance metrics and profiling tools.

Benefits

Full medical, dental, and vision packages, with generous premium coverage

Housing subsidy of $2,000 / month for those living within walking distance of the office

Daily lunch and dinner in our office

Relocation support for those moving to San Jose (Santana Row)

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Compensation Range : $150K - $275K

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