Piper Companies is seeking a Packet Processor Architect to join a fast-growing innovator in AI infrastructure, for an onsite permanent position in Saratoga, CA. The Packet Processor Architect will design and lead the development of high-performance packet processing hardware that powers fast, intelligent data movement across complex network systems.
Responsibilities of the Packet Processor Architect include:
Qualifications for the Packet Processor Architect include:
Compensation for the Packet Processor Architect:
Keywords: ASIC architecture, packet processing pipelines, hardware network protocols, RTL design, Verilog, SystemVerilog, high-speed networking, protocol offload engines, Network-on-chip, P4, programmable data planes, HBM, DDR, SRAM, TCP/IP, RoCE, NVMe-of, load balancing, QoS, NFV, L2 switching, L3 switching, L4 switching, routing, MACsec, ethernet MAC/PHY integration.
This job opens for applications on 7/2/. Applications for this job will be accepted for at least days from the posting date.
ASIC Packet Processing Architect • Saratoga, CA
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