Principal Design Verification ArchitectSamsung Electronics Perú • San Jose, CA, United States
Principal Design Verification Architect
Samsung Electronics Perú • San Jose, CA, United States
28 days ago
Job type
- Full-time
Job descriptionPosition Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role and Responsibilities We’re seeking a Principal Design Verification Architect to join our System IP team, where you will contribute to the functional verification of System IP, including coherent interconnect, caches, and dynamic memory controllers. As a senior-level individual contributor with technical leadership capabilities, you'll drive hands-on project execution and provide expertise in design verification. A strong background in Design Verification, test bench architecture skills, methodologies, and hands-on experience with both block-level and top-level is required to be successful in this role. You serve as the technical expert for verification know-how and micro-architecture You design and build reusable testbenches from scratch You identify and propose solutions to improve existing verification flows You architect next gen verification test benches and flows to boost productivity You develop and implement best practices to enhance productivity You own key features and execute tasks to meet milestones You create test plans, challenge specs, and review test plans / code You collaborate with designers to resolve spec issues and verify design correctness You develop verification environments, stimulus, and tests You debug and root cause functional fails from regressions You analyze code and functional coverage results, performing gap analysis You identify coverage exclusions and improve stimulus You collaborate with SoC, Physical Design, and Performance Verification teams to debug and resolve issues You help with Silicon debug issues You provide mentorship to junior team members Skills and Qualifications 20+ years of experience with a Bachelor’s degree in Computer Science / Computer Engineering / relevant technical field, or 18+ years of experience with a Master’s degree, or 16+ years of experience with a PhD 15+ years of industry experience in design verification Expert-level SystemVerilog and UVM coding skills Knowledge of ARM protocols (CHI, AXI, ACElite, APB) Experience with Git version control and Unix / Perl scripting Must have Coherent interconnect verification experience Familiarity with both coherent interconnect and LPDDR memory controllers (ideal) Strong written and verbal communication skills Formal verification skills (a plus) Our Team Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture. Total Rewards At Samsung – SARC / ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $221,700 and $364,800. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).Samsung employees have access to benefits including : medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.Additionally, this role might be eligible to participate in long term incentive plan and relocation. U.S. Export Control This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information. Trade Secrets By submitting an application, you [applicant] agree[s] not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.#SARC #ACL\ Please visit to see Privacy Policy, which defaults according to your location. You can change Country / Language at the bottom of the page. If you are European Economic Resident, please click .\ Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.
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Principal Architect • San Jose, CA, United States
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