DFT Lead opportunity to work for a Hardware company focused on accelerating training and infere[...]

Overview

DFT Lead

Full Time Opportunity in Saratoga, CA

Responsibilities

• Define the DFT architecture of a multi-chip system SOC. involving all aspects of test design functions such as Scan, BIST, Memory Repair, BSD ( ACJTAG / DCJTAG).
• Proficiency in Synthesis design constraints. ( Ie SDC)
• Prior experience with Serializers / Deserilizers.
• Sound Proficiency in either Mentor / Synopsys Test Tools required. Proficiency is synthesis,
• Define and implement OCC. Exposure to advanced DFT techniques like LBIST and streaming preferred.
• Fluent in RTL level and Gate level simulation.
• Supervise ATPG generation and achieve high coverage goals for scan and @speed scan.

Qualifications

J-18808-Ljbffr