Physical Design Engineer

Job Details :

The Custom SoC team develops next-generation Xeon-based solutions tailored for server, AI, and data center applications. In this role, you will collaborate with leading customers on high-visibility programs that shape the future of computing. You’ll join a world-class engineering team leveraging advanced design methodologies and cutting‑edge process technologies to deliver industry-defining products.

The role’s responsibilities include but are not limited to :

• Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power / clock distribution, reliability, and power and noise analysis.
• Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyzes results and makes recommendations to fix violations for current and future product architecture.
• Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
• Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications :

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Preferred Qualifications

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork / classes / research.

Business group : At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad‑market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general‑purpose compute, web services, HPC, and AI‑accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Job Type : Experienced Hire Shift : Shift 1 (United States of America) Primary Location : US, Texas, Austin Additional Locations : US, California, Santa Clara, US, Massachusetts, Beaver Brook

Position of Trust : N / A

Work Model for this Role

This role will require an on‑site presence. Job posting details (such as work model, location or time type) are subject to change.

Annual Salary Range for jobs which could be performed in the US :

$139,710.00-262,680.00 USD

Benefits :

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here : https : / / intel.wd1.myworkdayjobs.com / External / page / 1025c144664a100150b4b1665c750003

Posting Statement :

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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