Software Engineer, ML Performance

About Etched

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning.

Software Engineer, ML Performance

Running millions of tokens per second for large models (e.g Llama-3-70B) means running into new performance bottlenecks. Even with hardware optimization for the operations that usually bottleneck us (attention, kernel parallelism), we encounter novel bottlenecks and must design our own solutions to solve them.

You will work closely with our hardware and software teams to identify and mitigate performance bottlenecks, enabling our chips to achieve unprecedented throughput and efficiency. Your work will involve a blend of low-level programming, performance profiling, and hands-on debugging, all aimed at maximizing the performance of our custom-built AI hardware.

You will also play a key role in developing tools and methodologies to help our customers understand the full potential of our hardware.

Representative projects :

• Writing new kernels to improve throughput for LLM embedding
• Improving on PagedAttention to prevent fragmentation of the KV cache in memory
• Debugging hardware issues on a simulated or emulated chip
• Profile transformers running on our hardware, and fix bottlenecks
• Develop ways for customers to work with our chip and understand how their workloads will run on it.

You may be a good fit if you :

We encourage you to apply even if you do not believe you meet every single qualification.

Strong candidates may also have experience with :

How we're different :

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Benefits :