Senior RTL Design Engineer

We are hiring a Senior RTL Design Engineer to own memory subsystems in high-performance AI accelerators. This role will deliver the bandwidth, latency, and power profile needed for large-scale compute.

What you’ll do

• Architect and implement memory controllers for HBM2E / 3, LPDDR5 / 6, and DDR5.
• Deliver RTL from spec to tape-out : coding, simulation, synthesis, optimization.
• Integrate memory PHY, interposer, and DRAM interfaces into SoC.
• Collaborate with architecture, verification, and PD teams to close timing and power.
• Debug across pre- and post-silicon phases; ensure first-pass success.
• Contribute to other subsystems as gaps arise.

Skills & background

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Engineering and Design

Industries : Semiconductor Manufacturing and Computers and Electronics Manufacturing

The base pay range for this position is $190,000.00 / yr - $230,000.00 / yr.

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