Senior FPGA Engineer (Santa Clara County)

About the Role

The FPGA Verification Engineer will be responsible for ensuring the quality and reliability of our FPGA designs through rigorous verification processes. This role requires a strong background in SystemVerilog and UVM, along with hands-on experience in verification methodologies.

Responsibilities

• FPGAVerification Exp
• Strong SystemVerilog Coding (Universal Verification Methodology) - UVM
• 4+ years of FPGA verification experience
• Strong SystemVerilog programming skills
• Hands-on experience with UVM (Universal Verification Methodology)
• Familiarity with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS)
• Experience with code and functional coverage analysis
• Proficient in debugging and problem-solving
• Scripting experience in Python or Perl
• Knowledge of Verilog and / or VHDL