Senior Technical Staff Engineer - Design for Test in San Jose

Job Description

The DFT lead works in close partnership with different teams within the FPGA business unit spanning architecture, ASIC design, verification, physical implementation, and test engineering to implement the testability features into the combined FPGA and ASIC SOC. The DFT lead will be involved from the initial investigation and feasibility to tape‑out, as well as silicon validation and characterization of test methods on Automatic Test Equipment (ATE).

Responsibilities

• Manage DFT requirements across architecture, design, and product teams to ensure coverage, die cost, test cost and DFT integration requirements are met at the block and full chip level. Define, implement and validate DFT features at the FPGA full chip and sub‑systems level.
• Collaborate closely with cross‑functional teams to support DFT insertion, synthesis, scan insertion, place‑and‑route, static timing analysis, timing closure, power analysis during test and quantifying full chip test coverage.
• Establish and maintain DFT design and insertion guidelines and documents best practices for all development teams to follow.
• Be current with emerging technologies and methodologies in DFT and incorporate them into the FPGA to continuously improve test cost and quality.
• Work with Test and Product engineers to support development of firmware‑targeted test patterns, ATPG and mBIST test feature validation processes, and silicon debug activities.
• Communicate project status and progress to chip lead and engineering management.

Qualifications

Skills and Experience

Additional Information

Travel Time : 0% – 25%

Physical Attributes : Feeling, Handling, Hearing, Other, Seeing, Supervises Others, Talking, Works Alone, Works Around Others

Physical Requirements : 10% walking, 10% standing, 80% sitting; 100% in doors; Usual business hours

Pay Range : We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry‑leading ESPP program with a 2‑year look back feature. The annual base salary range for this position, which could be performed in California, is $88,000 – $232,000.

Microchip Technology Inc is an equal opportunity / affirmative action employer. All qualified applicants will receive consideration for employment without regard to protected Veteran status, or any other characteristic protected by law.

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