As a member of our CPU Cache Coherent Interconnects Design Team, you will be responsible for the physical design of CPU on‑chip interconnect network and last‑level caches, working on implementation, synthesis and timing closure while collaborating closely with the logic design team on micro‑architecture definition and feasibility. This position offers you the opportunity to have real impact in a dynamic, technology‑focused company impacting product lines ranging from consumer graphics to self‑driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
What you'll be doing :
What we need to see :
NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power‑efficient chips in their class? If so, we want to hear from you.
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Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 23, 2025. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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Asic Design Engineer • Santa Clara, CA, United States