Job Description
Job Description
Senior Verification Engineer
Also open to staff, principal, or senior principal level engineers!
Location : Suwanee, GA 30024 | Relocation assistance provided in form of a sign-on bonus
Hybrid Remote : 3 days in the office per week | Reporting To : Sr. Director, Engineering
Responsibilities :
- DDR5 DIMM system-level verification and PMIC IP verification
- Collaborating with component testing verification teams across global offices
- Interacting with design, product, and spec engineering teams internally
- Contributing to silicon debugging as needed
- Developing, driving, and implementing UVM SystemVerilog TestBench infrastructure
- Developing stimulus covering, SV assertions, and scripts as necessary
- Providing mentorship to junior engineers on the team
- Debugging regressions and failing simulations
Requirements :
5+ years of experience in verification engineering in the semiconductor industryUnderstanding of CMOS circuit design and experience building UVM Testbench from scratchStrong understanding of DDR5 protocol or CXL 2.0 specificationsExperience with digital and analog simulation tools : VCS, Xcellieum, VerdiCompensation :
$150K - $225K + Annual Bonus + Stock Options