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Senior Foundry Applications Engineer (ASIC Physical Design)

Senior Foundry Applications Engineer (ASIC Physical Design)

IntelSanta Clara, CA, United States
1 day ago
Job type
  • Full-time
Job description

Senior Foundry Applications Engineer (ASIC Physical Design)

Intel Foundry Services is engaged with customers today starting with our existing foundry offerings. We are expanding at a torrid pace to include our most advanced technologies, which are ideal for high-performance applications, and they are completely dedicated to the success of its customers with full profit and loss responsibilities. Using this model will ensure that our foundry customers' products receive our utmost focus in terms of service, technology enablement, and capacity commitments.

Responsibilities

  • Collaborate with internal teams across Intel and external stakeholders such as foundry customers' design teams, IP providers, and EDA vendors on issue resolution.
  • Create content, application notes and deliver technical training / presentations.
  • Drive quality of design kits and documentation through ASIC design reference flow validation and reviewing documentation.
  • Support and provide Tool / Flow / Methodology on customer issues and challenges for successful customer tape-outs, and to increase customer satisfaction.

Qualifications

Minimum Qualifications

  • US Citizenship required.
  • Ability to obtain a US Government Security Clearance.
  • Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
  • 5+ years of experience with advanced CMOS processes (16nm and below).
  • 4+ years of experience in ASIC physical design implementation and / or ASIC design signoff (SOC / ASIC).
  • 4+ years of experience in scripting languages like Python, Perl, Tcl, and / or shell scripting.
  • Preferred Qualifications

  • Active US Government Security Clearance with a minimum of Secret level.
  • Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
  • Hands?on experience in one or more areas of ASIC Design Implementation and methodology, Full chip Integration, Synthesis, APR, Static Timing Analysis, Layout Verification and Reliability Verification.
  • Experience with major EDA tools and flows and tools (Fusion Compiler, PrimeTime, PrimeECO, ICV) and / or Cadence Suite (Innovus, Tempus, TempusECO, Pegasus, Voltus).
  • Experience using hierarchical and multi-voltage domain design approach, top?down design, budgeting, timing and physical convergence, correlation across implementation and Verification Tools and building Quality Assurance (QA) regression.
  • Customer facing experience.
  • Experience in SOTA Process technology (7nm and below).
  • Location : US, Arizona, Phoenix

    All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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