System on Chip Architect (ASIC / RISCV)

System on Chip (SoC) Architect

Locations : Salt Lake City, UT or Boise, ID (On-site, Full-Time - Classified Program)

Security Requirement : Must be a US Citizen , ideally with active U.S. security clearance (or held within the last two years).

Our client develops secure, hardened system solutions-leveraging Client CPU designs, crypto cores, and purpose-built SoC architectures. These technologies are vital to safeguarding military systems and critical U.S. infrastructure against future threats.

Key Responsibilities

• Lead a cross-functional engineering team (hardware, software, verification) to drive the design and production of a RISC-V ASIC SoC , transitioning an existing RTL into a tape-out-ready, production-quality chip.
• Serve as the primary technical liaison between pilot customers, internal teams, and external subcontractors to define functionality, use cases, and specifications.
• Finalize and manage the microarchitecture definition , including specifications and verification plans covering performance, power, area, security, and cost.
• Design and oversee a thorough verification strategy (testbench, functional, and performance validation) to maximize first-pass success.
• Stay current with ASIC process and design advancements , integrating new methodologies where appropriate.
• Drive the product roadmap , translating feature requirements into actionable sprints and deliverables.
• Partner strategically with external collaborators to support development, marketing, and product sustainment.

Required Qualifications

Preferred Experience

Must-Haves

Recruiter Submission Template - SoC Architect (ASIC / RISC - V)

Full Name :

Degree & University (Year) :

Active or Recent Security Clearance (within 2 years) :

Total Years' experience in ASIC Design & Architecture :

Experience Designing & Fabricating ASICs :

RISC-V Architecture Expertise :

Total Years' experience RTL Coding (Verilog or VHDL) :

Total Years' experience ASIC Design Flow Expertise :

EDA Tool Experience :

Digital Logic / Clocking / Low-Power Design Knowledge :

Total Years' experience Verification Strategy (UVM / SystemVerilog) :

Total Years' experience Processor Architecture Knowledge :

Total Years' experience Applied Cryptography / Cybersecurity Experience :

Total Years' experience Cross-Functional Leadership :

Total Years' experience Product Roadmap & Delivery Experience :

Can you describe your experience leading the design and fabrication of an ASIC from RTL to production?

What is your experience with RISC-V or other processor architectures? Have you worked on CPU / SoC designs before?

Describe your proficiency with RTL coding (Verilog / VHDL) and EDA tools. Which synthesis, place-and-route, and timing closure tools have you used?

This role requires at least 8 years of ASIC design experience. Can you confirm you have 8 years of experience in ASIC development?

Are you legally authorized to work in the US, and would you be able to obtain a security clearance?

Describe your experience leading a cross-functional team (hardware, software, verification engineers) on an ASIC project.

Describe your most recent hands-on ASIC design and architecture project.

Contact Number : Email ID :

LinkedIn Profile (if available) :

Address (City, State, Zip) :

Notice Period :

Work Authorization Status :

Expected Salary :

Willing relocate on your own expenses and Work Onsite in Salt Lake City or Boise ?