ASIC Design Verification Engineer - Minneapolis, MN (Hybrid)

Job Title : ASIC Design Verification Engineer

Location : Minneapolis, MN (Onsite / Hybrid)

Duration : Full-Time

U.S. Citizens or U.S. Permanent Residents only

Required Qualifications

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline

Minimum of 7 years of hands-on experience in ASIC or SoC design and verification

Strong expertise in RTL design using Verilog / SystemVerilog

Proficiency in verification methodologies including UVM, constrained-random, and coverage-driven verification

Skilled in using EDA tools such as Synopsys Design Compiler, PrimeTime, VCS, Formality, and Mentor Questa / Tessent

Thorough understanding of DFT principles, including scan insertion

Experience working in UNIX / Linux environments with scripting languages such as Shell, Perl, Python, and TCL

Excellent communication abilities and a strong team-oriented approach