Job Description
Johns Creek, GA or San Jose, CA
About the Role
We are a leading provider of chip and silicon IP solutions, seeking an exceptional Senior Engineer with signal integrity and package design expertise to join our Memory Interface engineering team. This full-time role involves developing products that boost data speed and security. Reporting to the VP of Engineering, you'll focus on SI / PI modeling, analysis, and simulations for high-speed DDR applications up to 12800+ MT / s.
Key Responsibilities
Requirements
Qualifications
Benefits
If you're a technical expert in SI / PI, EM simulation, transmission lines, and lab tools like ADS / HFSS / PowerSI, apply now. Push high-speed memory boundaries with us!
Requirements
Qualifications MS / PhD in Electrical Engineering; 10+ years experience, including DDR4 / DDR5 focus. Experience simulating high-speed memory (DDR4 / DDR5) and / or SERDES. Strong in EM and transmission line theory. Expertise in equalization (FIR / FFE / DFE / CTLE). Proficient in package / PCB design : editing APD / Allegro files, SI / PI-driven BGA, system simulations. Hands-on correlation of simulations with lab measurements (scopes, TDRs, VNAs). Desirable : Server system knowledge (CPUs to DRAMs); crosstalk / jitter in source-synchronous interfaces for low BER. Skilled in Spice, ADS, HFSS, Q3D / PowerSI. Plus : RedHawk / Totem, XcitePI, Virtuoso familiarity. Valued : Lab experience with passive components, margins, noise (scopes, VNA / TDR). Preferred : Basic high-speed link circuit knowledge. Excellent communication, writing, presentation skills for customers / teams. Innovative, self-motivated team player with leadership.
Signal Integrity Engineer • San Jose, CA, us