Senior Design Verification Engineer

Qualitest seeking an experienced Design Verification Engineer to ensure the functional correctness, performance, and spec compliance of complex digital ASIC Core / IP designs. This role involves deep, unit-level, and core-level verification, requiring strong technical expertise and the ability to drive verification independently.

Location : Sunnyvale, CA — Onsite, Full-Time (5 days / week)

Key Responsibilities

• Plan : Develop detailed verification plans derived from micro-architecture and design specifications.
• Architect : Design and implement scalable, reusable SystemVerilog / UVM verification environments.
• Test : Create and run constrained-random and directed testcases to ensure high functional and code coverage.
• Debug : Analyze simulation results, diagnose complex issues, and work closely with RTL and micro-architecture teams to resolve bugs.
• Automate : Build and maintain automation scripts (Python / Perl) to improve verification efficiency and regression infrastructure.

Required Qualifications