Company : Qualcomm Technologies, Inc.
Job Area : Engineering Group, Engineering Group >
ASICS Engineering
General Summary :
We are seeking a highly skilled and motivated Physical Design Engineer to join our team. The ideal candidate will have hands‑on experience in RTL‑to‑GDSII flow, with a strong focus on floor‑planning, clock tree synthesis, place‑and‑route, DRC and timing closure. This role involves architecting and implementing robust, low‑skew, power‑efficient clock distribution networks tailored for a complex design to meet performance, power, and area goals. This role requires full‑time onsite work in San Diego, CA (5 days per week).
Minimum Qualifications :
Key Responsibilities :
Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry‑standard tools (e.g., Innovus, ICC2).
Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime).
Collaborate with RTL designers to resolve timing, congestion, and DRC issues.
Optimize design for power, performance, and area (PPA).
Conduct formal equivalence checks between RTL and netlist.
Support physical verification including DRC, LVS, and antenna checks.
Work closely with backend teams for tapeout preparation and signoff.
Excellent scripting skills (TCL, Python, Perl) for reference flow automation.
Execute full‑chip and block‑level physical verification including DRC, LVS, ERC, antenna, and density checks using industry‑standard tools (e.g., Calibre, Pegasus, ICV).
Customize and optimize reference physical verification flows to align with project needs and foundry requirements.
Perform GDS‑to‑GDS comparisons to validate ECO changes, ensure layout integrity, and support tapeout readiness.
Debug and resolve physical verification violations, working closely with layout, design, and CAD teams.
Collaborate with foundries to ensure compliance with latest design rule manuals (DRMs) and tapeout checklists.
Support signoff verification, including multi‑corner / multi‑mode analysis and ECO validation.
Develop and maintain automation scripts for verification flows, reporting, and regression testing.
Interface with EDA vendors to resolve tool issues and improve flow robustness.
Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability.
Ensure timely delivery of clean GDSII for tapeout, with full verification signoff.
Perform full‑chip and block‑level static timing analysis (STA) using industry‑standard tools (e.g., Synopsys PrimeTime, Cadence Tempus).
Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners.
Collaborate with RTL, synthesis, and physical design teams to ensure timing‑aware design practices.
Debug and resolve setup, hold, and transition violations across various PVT corners.
Drive timing closure through iterative optimization and ECO implementation.
Customize and enhance timing analysis flows to improve accuracy, efficiency, and scalability.
Analyze clock tree timing, including skew, latency, and jitter impacts.
Support signoff timing verification, including cross‑domain timing and false / multicycle path handling.
Interface with EDA vendors to resolve tool issues and improve flow robustness.
Participate in design reviews, providing insights on timing risks and mitigation strategies.
Define and implement low‑power architecture using CLP methodology across RTL and physical design stages.
Develop and maintain power intent files (UPF / CPF) and ensure alignment with design specifications.
Customize and optimize low‑power reference flow to meet project‑specific requirements.
Collaborate with RTL, synthesis, and physical design teams to integrate power‑aware features such as power gating, retention, isolation, and level shifting.
Perform power‑aware static checks, simulation, and formal verification to validate power intent.
Debug and resolve issues related to power domain crossings, voltage islands, and power sequencing.
Support signoff verification including power‑aware LVS / DRC, STA, and EM / IR analysis.
Interface with EDA vendors to resolve tool issues and improve low‑power flow robustness.
Participate in design reviews, providing insights on power architecture, risks, and mitigation strategies.
Ensure compliance with foundry low‑power guidelines and contribute to successful tapeout.
Qualifications :
Preferred Skills :
Principal Duties & Responsibilities :
Level of Responsibility :
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EEO Employer :
Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
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Pay range And Other Compensation & Benefits :
$115,600.00 - $173,400.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
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Senior Design Engineer • San Diego, CA, United States