IC Layout Design Engineer (TSMC FinFET)

IC Layout Designer

Full-time + Benefits

US Citizen or US Permanent Resident

Richardson, Texas (onsite / hybrid) or remote / from any US location

Requirements

• 3+ years of experience in Cadence layout (Virtuoso, VXL) and Calibre verification (ERC, DRC, LVS)
• 3+ years of experience in layout and verification tools and methodologies for RF / Analog / Mixed-Signal ICs
• BSEE or AA degree
• TSMC FinFET experience in advanced technology nodes (7nm and below)
• Comprehensive understanding of matching, shielding, guard rings and latch up
• Debugging and analytical skills with complex technical concepts
• Demonstrated success in delivering quality work product
• Experience in DFM hierarchical layout construction for efficient verification and integration
• Must understand techniques for managing layout dependent effects i.e. IR drop, RC delay, electron-migration, self-heating and crosstalk
• Proficiency in PERL or SKILL scripting is a plus
• Strong verbal and written communication

IC MASK LAYOUT DESIGN GROUP on LinkedIn :

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