ASIC Power Engineer (Design Engineer V)

Role

ASIC Power Engineer

DUTIES

ASIC Power Engineer to perform power analysis and optimizations in ASIC for Metaᅡᆲ ̄ツ ̄텖s AR / VR products. Areas of interests includes Machine Learning. Primary languages are Python, tcl and SystemVerilog.

RESPONSIBILITIES

• Perform PPA optimization with Fusion compiler.
• Perform RTL and netlist level Power analysis.
• Perform post-processing and scripting on report log files for format conversion, data analysis and information extraction.
• Setup, run, debug and analyze reports of ASIC flows (Synthesis, PD, Power, Timing).
• Implement some blocks at RTL and UPF.
• Ability to document and communicate clearly.

MINIMUM QUALIFICATIONS

PREFERRED QUALIFICATIONS

EEO

ᅡᆲ ̄ツ ̄텚Mindlance is an Equal Opportunity Employer and does not discriminate in employment on the basis of ᅡᆲ ̄ツ ̄테ᄁ Minority / Gender / Disability / Religion / LGBTQI / Age / Veterans.ᅡᆲ ̄ツ ̄테ᄈ

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